The exemplary embodiments described herein relate generally to semiconductor devices and methods for the fabrication thereof and, more specifically, to semiconductor devices utilizing three-dimensional stacking architectures to form dense logic gates and static random access memory (SRAM) cells.
Static Random Access Memory (Static RAM or SRAM) is a type of semiconductor memory that uses bistable latching circuitry (flip-flop circuitry) to read, write, or store one bit of data. Each of the two stable states characterize values corresponding to “0” and “1.” The one bit of stored data is held in a static form and is considered volatile in the sense that the data is lost when the memory is no longer powered.
In an SRAM cell, an arrangement of transistors is used to carry out the read, write, and store operations. For example, in a six transistor (6T) SRAM cell, a core is formed by two pairs of transistors, each pair forming an inverter, in which the output potential of each inverter is fed as the input potential to the other inverter to form a feedback loop that stabilizes the inverters to their respective states. The inverters allow for the storage of the one bit of data. The other two transistors are access transistors that provide access to the stored data for the read and write applications. The access transistors are each coupled to a word line and bit lines. Upon the application of voltages through the word line and bit lines, the states of the inverters and access transistors are switched on or off, thus directing the SRAM cell to read, write, or store data.
The transistors may be arranged using three-dimensional stacking schemes to increase the densities of the architectures that form the SRAM cells. However, these stacking schemes generally employ wafer stacking or SIMOX processes (separation by implantation of oxygen). Such stacking or SIMOX processes are typically costly and do not permit tight vertical stacking to form logic gates and SRAM cells having the desired densities.